Systems and Methods for a Thin Film Capacitor Having a Composite High-K Thin Film Stack

ABSTRACT

Systems and methods are provided for fabricating a thin film capacitor involving depositing an electrode layer of conductive material on top of a substrate material, depositing a first layer of ferroelectric material on top of the substrate material using a metal organic deposition or chemical solution deposition process, depositing a second layer of ferroelectric material on top of the first layer using a high temperature sputter process and depositing a metal interconnect layer to provide electric connections to layers of the capacitor.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and is related to U.S. ProvisionalPatent Application No. 60/917,371, filed on May 11, 2007, the entiretyof which is incorporated herein by reference.

FIELD

The technology described in this patent document relates generally tothe field of thin film devices and fabrication. More particularly, thepatent document describes a composite high-k thin film stack forimproving the time-dependent dielectric breakdown (TDDB) of a thin filmcapacitor.

BACKGROUND

Ferroelectric capacitors have potential use as decoupling orvoltage-tunable capacitors (varactors) in RF systems. Some benefits offerroelectric capacitors are small size, integration of different valuesand functions of capacitance, and low cost. Applications forferroelectric capacitors may include tunable filters, voltage-controlledoscillators, tunable phase shifters, tunable matching networks,low-impedance power supplies, decoupling high-frequency signals at an ICbonding pad, or others. Integrated circuits including ferroelectriccapacitors may, for example, be used in portable electronics forlow-power wireless communication (e.g., cellular phones, pagers, PDAs,etc.), directional antenna systems, high clock-rate microphones,miniature DC to DC converters, or other devices.

A ferroelectric capacitor may be fabricated by depositing aferroelectric film on an electrode layer and then depositing a secondelectrode layer over the ferroelectric film. The deposition techniquecan be sputtering, chemical vapor deposition (CVD) of any kind(including ALD and CCVD), or pulsed laser deposition (PLD). Theferroelectric film can be Barium Strontium Titanate (BST), StrontiumBismuth Tantalate (SBT), Lead Zirconate Titanate (PZT), Lead LanthanumZirconate Titanate (PLZT) or any other perovskite or pyrochlore phaseferroelectric film or a combination thereof. The electrode can be madeof any metal or conductive oxide or any combination of these materials.Preferred in this embodiment is Platinum, Platinum alloy, Iridium eithersolely or in combination with Iridium Oxide, Ruthenium Oxide, orStrontium Ruthenium Oxide (SRO). Sputtered ferroelectric films have acolumnar morphology with a pronounced preferential orientation that isperpendicular to the electrodes. As a result, sputter depositedperovskite films have a high tuning and capacitance density. However,the TDDB behavior of the ferroelectric capacitor is adversely affectedby the crystalline columnarity of the ferroelectric film because grainboundaries are aligned perpendicular to the electrodes. The technologydescribed herein provides a modification to the columnarity of thesputtered ferroelectric film, which breaks up charged carrier migrationthrough the film and thus improves the TDDB of the capacitor.

SUMMARY

A capacitor structure is provided that includes a first electrode layerof conductive material, a dielectric formed from a ferroelectric layerdeposited in a manner that forms a columnar grain structure and aferroelectric layer deposited in a manner that forms a randomly-orientedgrain structure, and a second electrode layer of conductive material ontop of the dielectric layer.

Additionally, a tunable thin film capacitor structure is providedincluding a first electrode layer of conductive material, aferroelectric seed layer having randomly distributed grains deposited ontop of the first electrode layer, a high temperature sputter applieddielectric layer deposited on top of the seed layer, and a secondelectrode layer of conductive material on top of the dielectric layer.

Further, a method for fabricating a thin film capacitor is provided thatincludes depositing an electrode layer of conductive material on top ofa substrate material, depositing a first layer of ferroelectric materialon top of the substrate material in a manner that forms arandomly-oriented grain structure, depositing a second layer offerroelectric material on top of the first layer using a hightemperature sputter process in a manner that forms a columnar-orientedgrain structure, and depositing a metal interconnect layer to provideelectric connections to layers of the capacitor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts an example ferroelectric capacitor that includes a thinseed layer between the lower electrode and the dielectric layer.

FIG. 2 depicts another example ferroelectric capacitor that includes athin seed layer.

FIG. 3 depicts an example process for fabricating a multilayer capacitorstructure.

FIG. 4 is a flow diagram depicting the process of fabricating amultilayer capacitor structure.

DETAILED DESCRIPTION

The columnarity of a ferroelectric film may be modified by depositing avery thin layer (seed layer) of a ferroelectric material with randomlydistributed grains prior to the sputter deposition of the ferroelectricfilm. The ferroelectric seed layer with randomly distributed grains maybe deposited using any kind of Metal Organic Deposition (MOD) orChemical Solution Deposition (CSD) technology. The deposition method canbe either spin-on or misted deposition with subsequent thermalprocessing. Thermal processing may include hot plate bakes, oven bakes,rapid thermal processing (RTP), vacuum bakes (including in-situ bakewhile sputtering) or high temperature anneals. The ferroelectric film isthen deposited over the thin seed layer using one of the depositionmethods mentioned above. In this manner, the randomly distributed grainsin the seed layer will distort the preferred orientation of crystallinecolumnarity in the deposited ferroelectric film and also interrupt thevertically-oriented grain boundaries resulting in an improvement in theTDDB behavior of the capacitor.

FIG. 1 depicts an example ferroelectric capacitor 10 that includes athin seed layer 12 between the lower electrode 14 and the dielectriclayer 16. The capacitor structure 10 includes two conducting electrodes14, 18 that are separated by the thin seed layer 12 and the dielectriclayer 16. The conducting electrodes 14, 18 may, for example, befabricated using platinum or a platinum alloy. The seed layer 12 isfabricated by depositing a thin layer of ferroelectric material (e.g.,BST) on the lower electrode 14, for example using MOD technology (e.g.,spin coating). The seed layer 12 should preferably be as thin aspossible because a thick seed layer may adversely affect the operationof the capacitor 10. The dielectric layer 16 is fabricated by depositinga ferroelectric material, such as BST, using a high temperature sputterprocess. The capacitor 10 may, for example, be fabricated on a substratematerial coated with one or more insulating layers (not shown).

As described above, the thin seed layer 12 distorts the orientation ofcrystalline columnarity in the sputtered (CVD or PLD deposited)ferroelectric film 16 resulting in improved TDDB behavior of thecapacitor 10. In addition, the thin seed layer 12 may heal and planarizepossible defects and roughness in the electrode 14 such that thesputtered (or other columnar) film 16 is deposited onto a very smoothand defect free surface. A low temperature MOD seed layer 12 may protectthe electrode 14 during the high temperature sputtering process,preventing possible damage (e.g., increased roughness, etc.) Acombination of an undoped BST and a doped BST formulation, or acombination of different ferroelectric materials may also be beneficialin other ways, such as minimizing the space charge, and improving thetemperature dependence of dielectric properties.

FIG. 2 depicts another example ferroelectric capacitor 20 that includesa thin seed layer 22. In this example, the thin seed layer 22 isdeposited between two columnar dielectric layers 24, 26. A firstferroelectric layer 24 is deposited on a lower electrode 28. The seedlayer 12 is then fabricated by depositing a thin layer of theferroelectric material (e.g., BST or other ferroelectric with randomlydistributed grains) on the first columnar-oriented ferroelectric layer24, for example using MOD technology. A second columnar-orientedferroelectric layer 26 is fabricated by a deposition technique such assputtering over the seed layer 22. An upper electrode 30 is thenfabricated over the upper dielectric layer 26 to form the capacitorstructure 20.

The fabrication processes described above with reference to FIGS. 1 and2 may be repeated to form multi-layer capacitor structures. An exampleprocess for fabricating a multi-layer capacitor structure is illustratedin FIG. 3. In step 50 (FIG. 3A), one or more insulating layers 60 aredeposited on a substrate material 62. The substrate 62 may, for example,be Silicon, Alumina (including glazed and ZTA), Sapphire, SiliconCarbide, Magnesium Silicate (including Foresterite) or any other type ofinsulating, semi-insulating or semi-conducting material. The insulatinglayers 60 may include an insulating layer such as SiO₂ and a hermeticinsulating layer, such as Si₃N₄.

In step 52 (FIG. 3B), multiple capacitor layers 64 are fabricated on topof a deposited electrode layer 66, for example using the processdescribed above with reference to FIG. 1. In this example, two capacitorlayers 64 are illustrated, each having a 0.06 um MOD seed layer of BST68 and a 0.23 um layer of sputtered BST 70 deposited over the seed layer68. In step 54 (FIG. 3C), the capacitor layers 64 are patterned to forma mesa structure, such that each electrode layer 66 is accessible. Instep 56 (FIG. 3D), a planarizing and insulating layer 72 (e.g., an ILDglass layer) is deposited, patterned and etched to form vias 74. In step58 (FIG. 3E), a metal interconnect layer 76 is deposited that providesan electrical connection to the electrodes. A nitride overcoat 78 isdeposited to protect the metal interconnect layer 76 and gold bumps 80are deposited to provide electrical contacts for final packaging. A topview of the capacitor structure depicting the mesa shaped capacitorlayers 74, is also illustrated in FIG. 3F.

Tests of the capacitor structure shown in FIGS. 3A-3F demonstrated anincrease in the lifetime of the BST capacitors by at least one order ofmagnitude at accelerated stress conditions of 125-150 C and 83-100 V/um.For instance, under stress conditions of 125 C and 85V/um, wafersfabricated using this process had no TDDB failures over 1500 hours oftesting, while a wafer processed using the standard procedure (i.e. asputtered BST film with no seed layer) had all devices fail, with anaverage lifetime of 83 hours.

FIG. 4 is a flow diagram depicting an example process of fabricating amultilayer capacitor structure. At step 100 where an electrode layer ofconductive material is deposited. This electrode layer may be depositeddirectly onto a substrate or may be deposited onto a substrate that haspreviously had an insulating layer deposited.

Following deposition of the electrode layer in step 100, a first layerof ferroelectric material is deposited on top of the layer of conductivematerial in step 110. This layer of ferroelectric material heals andplanarizes possible defects and roughness in the electrode layer. Thefirst layer of ferroelectric material may be deposited using any kind ofMetal Organic Deposition (MOD) or Chemical Solution Deposition (CSD)technology. Examples of these technologies are spin-on deposition andmisted deposition. This first layer of ferroelectric material may have arandomly oriented grain structure that will distort the preferredorientation of the crystalline columnarity in the depositedferroelectric film and also interrupt the vertically-oriented grainboundaries resulting in an improvement in the TDDB behavior of thecapacitor.

The previously referred to second layer of ferroelectric material isdeposited on top of the first layer of ferroelectric material in step120. This second layer of ferroelectric material is deposited using ahigh temperature sputter process and may have a columnar oriented grainstructure as previously described. The steps of depositing the firstlayer of ferroelectric material 110 and depositing the second layer offerroelectric material 120 may be repeated as desired to form severalcapacitor layers as shown in step 125.

Once the desired number of capacitor layers have been deposited, thedeposited capacitor layers may be patterned into a mesa structure instep 130. Patterning the capacitor layers into a mesa structure offersaccess to all electrode layers and capacitor layers for later appliedstructures.

In step 140, a planarizing and insulating layer is deposited on top ofthe previously deposited layers. The planarizing and insulating layer isetched to form a set of pathways or vias in the capacitor structure.These etched vias offer conduits for metal interconnection materials tobe deposited in step 150.

Following deposition and etching of the planarizing and insulating layerin step 140, one or more metal interconnect layers are deposited in step150. This metal interconnect layer creates the electrical connections tothe previously deposited structures in steps 100-140. Followingdeposition of the metal interconnect layer, an additional layer ofprotective material such as a nitride overcoat may be deposited on topof the metal interconnect layer and gold bumps may be attached to themetal connections to help protect the previously deposited structures.

This written description uses examples to disclose the invention,including the best mode, and also to enable a person skilled in the artto make and use the invention. The patentable scope of the invention mayinclude other examples that occur to those skilled in the art.

1. A capacitor structure, comprising: a first electrode layer ofconductive material; a dielectric layer formed from a ferroelectriclayer deposited in a manner that forms a columnar grain structure and aferroelectric layer deposited in a manner that forms a randomly-orientedgrain structure; and a second electrode layer of conductive material ontop of the dielectric layer.
 2. The capacitor structure of claim 1,wherein the ferroelectric layer having randomly-oriented grain structuredistorts the grain structure of the ferroelectric layer having acolumnar grain structure.
 3. The capacitor structure of claim 1, whereinthe ferroelectric layer having randomly-oriented grain structureinterrupts vertically-oriented boundaries between the grains of theferroelectric layer having a columnar grain structure.
 4. The capacitorstructure of claim 1, wherein the ferroelectric layer havingrandomly-oriented grain structure is between the first electrode and theferroelectric layer having a columnar grain structure.
 5. The capacitorstructure in claim 1 where the ferroelectric layer withrandomly-oriented grain structure is between the ferroelectric layerhaving a columnar grain structure and a second ferroelectric layerhaving a columnar grain structure.
 6. The capacitor structure of claim1, wherein the ferroelectric layer having randomly-oriented grainstructure is between the second electrode and the ferroelectric layerhaving a columnar grain structure.
 7. The capacitor structure of claim1, wherein there are multiple layers of randomly oriented ferroelectriclayers and layers deposited in a manner that forms a columnar grainstructure.
 8. The capacitor structure of claim 1, wherein the layer withrandomly-oriented grain structure is of a different composition than thelayer with a columnar grain structure.
 9. A multi-layer capacitorstructure formed from two or more capacitor structures of claim 1stacked on top of each other.
 10. A tunable thin film capacitorstructure, comprising: a first electrode layer of conductive material; aferroelectric seed layer having randomly distributed grains deposited ontop of the first electrode layer; a high temperature sputter applieddielectric layer deposited on top of the seed layer; and a secondelectrode layer of conductive material on top of the dielectric layer.11. The tunable thin film capacitor structure of claim 10, wherein theseed layer is deposited by a misted deposition or a dip coating.
 12. Thetunable thin film capacitor structure of claim 10, wherein the seedlayer is a spin applied seed layer.
 13. The tunable thin film capacitorstructure of claim 10, wherein the seed layer is comprised of BariumStrontium Titanate.
 14. The tunable thin film capacitor structure ofclaim 13, wherein the dielectric layer is comprised of a ferroelectricmaterial selected from the group consisting of: Barium StrontiumTitanate, Strontium Bismuth Tantalate, Lead Zirconate Titanate, and LeadLanthanum Zirconate Titanate.
 15. The tunable thin film capacitorstructure of claim 14, wherein the electrode is comprised of a metal orconductive oxide selected from the group consisting of: Platinum,Platinum alloy, Iridium, Iridium and Iridium Oxide, Iridium andRuthenium Oxide, and Iridium and Strontium Ruthenium Oxide.
 16. Thetunable thin film capacitor structure of claim 10, further comprising asecond high temperature sputter applied dielectric layer depositedbetween the first electrode layer and the seed layer.
 17. The tunablethin film capacitor structure of claim 10, further comprising one ormore additional alternating ferroelectric seed layers and hightemperature sputter applied dielectric layers between the firstelectrode layer and the second electrode layer.
 18. The tunable thinfilm capacitor structure of claim 10, wherein the tunable thin filmcapacitor is fabricated on a substrate material coated with one or moreinsulating layers.
 19. The tunable thin film capacitor structure ofclaim 10, wherein the seed layer planarizes the first electrode layer.20. A method for fabricating a thin film capacitor, comprising:depositing an electrode layer of conductive material on top of asubstrate material; depositing a first layer of ferroelectric materialon top of the substrate material in a manner that forms arandomly-oriented grain structure; depositing a second layer offerroelectric material on top of the first layer using a hightemperature sputter process in a manner that forms a columnar-orientedgrain structure; and depositing a metal interconnect layer to provideelectric connections to layers of the capacitor.
 21. The method of claim20, further comprising depositing one or more sets of additionalalternating layers of ferroelectric material using a metal organicdeposition or chemical solution deposition process and ferroelectricmaterial using a high temperature sputter process before depositing themetal interconnect layer.
 22. The method of claim 20, further comprisingpatterning the first and second layers to form a mesa structurefollowing depositing the first and second layers.
 23. The method ofclaim 22, further comprising: depositing a planarizing and insulatinglayer following the patterning of the first and second layers; andetching the planarizing and insulating layer to form vias.
 24. Themethod of claim 23, wherein the metal interconnect layers are depositedin the formed vias to provide electric connections to layers of thecapacitor.
 25. The method of claim 20, wherein the first layer offerroelectric material is deposited by a spin-on process.
 26. The methodof claim 20, wherein the first layer of ferroelectric material isdeposited by a misted deposition process.
 27. The method of claim 20,wherein the first layer of ferroelectric material is comprised of BariumStrontium Titanate.
 28. The method of claim 20, wherein the first layerof ferroelectric material is deposited such that the first layer offerroelectric material planarizes the first electrode layer.
 29. Themethod of claim 20, wherein the first layer of ferroelectric material isdeposited by a metal organic deposition process.
 30. The method of claim29, wherein the first layer of ferroelectric material is deposited by achemical solution deposition process.
 31. The method of claim 29,wherein the first layer is of a different composition than the secondlayer.
 32. The method of claim 24, further comprising depositing aninsulating layer onto the substrate material before depositing the firstlayer of ferroelectric material.
 33. The method of claim 20, wherein thefirst layer of ferroelectric material is deposited about 0.06 μm inthickness.
 34. The method of claim 20, wherein the second layer offerroelectric material is deposited about 0.23 μm in thickness.
 35. Themethod of claim 20, wherein the second layer of ferroelectric materialis deposited such that the second layer is about six times as thick asthe first layer of ferroelectric material.